Due to advancements in processing technology, complex integrated circuits (ICs) can be designed at various levels of abstraction. Using a hardware description language (HDL), circuits can be designed at the gate level, the register transfer level (RTL), and/or higher logical levels. When designing using an HDL, the design is often structured in a modular manner. The designer describes a module in terms of the generation and propagation of signals from one set of registers through combinatorial modules to another set of registers. HDLs provide a rich set of constructs to describe the functionality of a module. Modules may be combined and augmented to form even higher level modules.
To reduce design costs, designers often incorporate previously created designs that have been provided either from within an enterprise or from a commercial provider. Libraries of pre-developed blocks of logic have been developed that can be selected and included in a circuit design. Such library modules include, for example, adders, multipliers, filters, and other arithmetic and digital signal processing (DSP) functions from which system designs can be readily constructed. These previously created designs are sometimes referred to as “IP cores” (intellectual property cores), or “logic cores,” and such terms may be used interchangeably herein. The use of pre-developed logic cores permits faster design cycles by eliminating the redesign of circuits. Thus, using cores from a library may reduce design costs.
Prior to implementation, an HDL design can be simulated to determine whether the design will produce correct output. By detecting errors early in the development cycle, wasted manufacturing costs due to faulty design may be avoided. In addition, it may be desirable to analyze performance attributes such as speed, power consumption, etc. One such attribute is susceptibility to single event upsets (SEU). SEUs occur as a result of fast-moving subatomic particles that interact with silicon atoms. When a single ion or neutron strikes a silicon substrate, it loses energy through the creation of free electron hole pairs. This results in a dense ionized track in the local region and a current pulse that can upset the circuit. The current pulse may or may not affect the circuit, depending on the switching behavior of the logic circuits in the circuit design. Thus, different portions of a circuit design may be more susceptible than others. If high-risk portions of a circuit design can be identified early in the design cycle, a designer may be able to mitigate the susceptibility through various design choices.
Precise measurement of switching activity requires test vectors, i.e., sample data that is used by the circuit design. Test vectors can be difficult to develop and may not fully exercise the circuit design. Further, an estimate of switching activity may be required early in the design process in order to be able to select from among alternative designs for a low-power design or high-reliability design. However, early in the design process, the circuit design may not be sufficiently complete to run test vectors, so a method of estimating switching activity without required test vectors is desirable.
One or more embodiments of the disclosure invention may address one or more of the above issues.